CHIP TAPEOUT

• Tool access & login setup
• Environment configuration
• Synopsys tool launch (DC, Fusion Compiler, VCS, Verdi, PrimeTime, StarRC)
• Lab infrastructure walkthrough

VLSI Flow Introduction (RTL to GDSII)

• RTL → GDSII flow (Frontend & Backend)
• Flat design flow (single-level netlist)
• Hierarchical design flow (block partitioning, scalability)
• Logic synthesis overview
• Timing optimization basics
• Floorplan, power plan, placement, routing overview

PDK & Input/Output Files (PDK Demystified)

• LIB (.lib), LEF/DEF
• Verilog & gate-level netlist
• SDC, SDF, SPEF
• SPICE netlist, UPF (power intent)
• Tech file, ITF, TLU+, NXTGRD

UNIX, TCL & Scripting

• UNIX fundamentals: File system, permissions
• Commands: grep, awk, sed
• Shell scripting basics
• TCL scripting: Variables, loops, procedures
• Usage in Synopsys tools (DC, ICC2, Fusion Compiler)

Digital Design using Verilog

• Combinational vs Sequential logic
• Verilog HDL: Syntax, data types, operators
• RTL design methodology
• Flat vs Hierarchical RTL

CMOS Fundamentals & Fabrication

• Semiconductor fundamentals
• MOSFET operation (NMOS/PMOS)
• CMOS inverter: VTC, noise margins
• Fabrication flow: Lithography, implantation, metallization
• PVT corners

Circuit Design & Layout

• CMOS logic design: Pull-up/pull-down networks
• Stick diagrams
• Layout fundamentals: Poly, diffusion, metal layers
• Design rules (lambda-based)
• Parasitic effects (RC delay)

Verification Concepts

• DRC / LVS
• SPICE simulations

STA Fundamentals

• Input/output formats (LIB, LEF, DEF, SDC, SPEF)
• Timing paths & delay modelling
• Timing arcs & LIB understanding
• Setup/Hold checks
• Clock concepts: Skew, latency, jitter
• SDC constraints & Timing closure basics

Low Power & Multi-Domain Design

• Dynamic vs static power
• Clock gating, power gating, Multi-Vt cells
• Multi-Domain Design: Voltage & Clock Domains
• CDC (Clock Domain Crossing) & Metastability

Logic Synthesis (Design Compiler → Fusion Compiler)

• Flat vs Hierarchical Design Flow
• RTL to gate-level mapping
• Optimization techniques: Area, timing, power trade-offs
• Technology mapping and libraries

Floorplanning

• Utilization, aspect ratio
• Macro placement
• Block-level & SoC level floorplanning
• Pin placement & Flylines

Power Planning

• Power rings, stripes, mesh
• Macro connections
• Multi-voltage domains

Placement

• Standard & physical-only cells
• Tap, tie, endcap cells
• Global placement & legalization
• Congestion handling

Clock Tree Synthesis (CTS)

• Clock Skew, jitter, latency
• H-tree, mesh structures
• NDR Rules
• Concurrent optimization

Routing

• Global & detailed routing
• Routing tracks & pitch
• Congestion challenges

Parasitic Extraction

• RC modelling
• SPEF generation
• TLU+, NXTGRD concepts

Timing Signoff (PrimeTime)

• Advanced STA concepts
• Signal integrity (crosstalk)
• ECO-based timing fixes

DFM & Tapeout

• Manufacturability basics
• Tapeout checklist
• Final GDSII generation

• Full Flow Execution: RTL → GDSII integration, Hierarchical design execution
• Debugging & Optimization: QoR improvement, Timing & congestion fixes
• Mentor Reviews: Design validation, Flow corrections

• Project Closure & Optimization
• Reporting & Documentation
• Interview Readiness: Mock interviews, Resume preparation
• Final Evaluation: Project review (RTL → GDSII), Technical viva